last highlighted date: 2023-02-03
Highlights
- Several other design layouts may or may not negatively impact SI but will most likely affect EMC. As a minimum, these important EMC (but not SI) design criteria include: Placement of high-threat clock/high-speed circuitry next to I/O circuitry; Routing of clock traces away from the edge of the board; Placement of I/O connectors on opposite sides of the board; Placement of high-speed traces between the I/O connector and I/O circuitry; Use of ground floods on signal layers; Routing of clock traces on surface layers; Use of decoupling capacitors; Proper heatsink grounding; Proper grounding of PCB mounting holes; and Overlapping clock harmonics and use of spread-spectrum clocks…